Receiver circuits, such as serializer/deserializer (SERDES) circuits, are ubiquitous in many computational environments. For example, in computational environments having high-speed data channels, a transmitter sends data as a signal across a channel, and a receiver receives the signal from the channel and seeks reliably to recover the data from the signal. Some receiver circuits include a direct-current-coupled (DC-coupled), or common-mode-matched, input. However, common mode variation and other issues can tend to frustrate reliable operation of such implementations. Recently, it has become more common for receiver circuits to include an alternating-current-coupled (AC-coupled) input. Such implementations typically include a DC blocking capacitor for removing common-mode from the differential data signal, and the DC blocking capacitor is typically implemented on the receiver die. Area limitations on the die tend to limit the size of the capacitor, and use of such smaller capacitors can tend to result in a high pole frequency for the receiver. The high pole frequency can cause the baseline of the received data signal to wander as a function of the data pattern.